Analysis and Comparison of Sigma Delta A/D Converter Model for AMS-VHDL and SIMULINK

This paper presents a simulation of sigma-delta A/D converter using mixed signal environment and compares the accuracy achieved by mixed signal modeling environment over normal simulators, the converter designed here is of third order, we also analyzed the behavior of the converter the complete simulation is performed using Simplorer VHDL– AMS simulator in which codes are written in VHDL–AMS language and compared it with SIMULINK model on the basis of mean squared error, and frequency response. Keywords— VHDL-AMS, Sigma Delta Converters, Mixed Signal Modeling.